Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Physical CAD changes to incorporate design for lithography and manufacturability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Post-routing redundant via insertion for yield/reliability improvement
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimal post-routing redundant via insertion
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 international symposium on Physical design
Redundant via insertion with wire bending
Proceedings of the 2009 international symposium on Physical design
Crosstalk- and performance-driven multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-Chip Routing Considering Double-Via Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
While via failure significantly contributes to yield loss during manufacturing, post-routing redundant via insertion method is the conventional means of reducing the via failure rate, but only alive vias can be protected. As existing dead vias still lower manufacturing yield, identifying a routing result with fewer dead vias can increase the redundant via insertion rate, subsequently enhancing the yield of chips. This work presents, for the first time, a redundant-via-aware routing system to retain redundant via resources in track assignment, in which redundant vias are inserted in detailed routing. The proposed via prediction scheme performs trial route using L-shaped patterns to estimate via positions. Meanwhile, the proposed redundant-via-aware detailed router gradually relaxes the limitation on the number of generated dead vias during path searching to minimize the number of dead vias. Experimental results indicate that the proposed redundant-via-aware routing system is, to our knowledge, the first routing system that can achieve 100% redundant via insertion rate with all MCNC benchmark circuits.