Fast algorithm for optimal layer assignment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Detailed layer assignment for MCM routing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
An efficient approach to multilayer layer assignment with an application to via minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of the maximum delay of global interconnects during layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing- and crosstalk-driven area routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Advanced routing in changing technology landscape
Proceedings of the 2003 international symposium on Physical design
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Timing driven track routing considering coupling capacitance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Crosstalk-aware routing resource assignment
Journal of Computer Science and Technology
Multilevel routing with jumper insertion for antenna avoidance
Integration, the VLSI Journal
Escape routing for dense pin clusters in integrated circuits
Proceedings of the 44th annual Design Automation Conference
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Priority-based routing resource assignment considering crosstalk
Journal of Computer Science and Technology
A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing
Journal of Discrete Algorithms
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dead via minimization by simultaneous routing and redundant via insertion
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Track routing optimizing timing and yield
Proceedings of the 16th Asia and South Pacific Design Automation Conference
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
GDRouter: interleaved global routing and detailed routing for ultimate routability
Proceedings of the 49th Annual Design Automation Conference
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Stitch-aware routing for multiple e-beam lithography
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
Routing is one of the most complex stages in the back-end design process. Simple routing algorithms based on two stages of global routing and detailed routing do not offer appropriate opportunities to address problems arising from signal delay, cross-talk and process constraints. An intermediate stage of track assignment between global and detailed routing proves to be an ideal place to address these problems. With this stage it is possible to use global routing information to efficiently address these problems and to aid the detailed router in achieving the wiring completions. In this paper we formulate routing as a three stage process; global routing, track assignment and detailed routing. We describe the intermediate track assignment problem and suggest an efficient heuristic for its solution. We introduce cost metrics to model basic effects arising from connectivity. We discuss extensions to include signal integrity and process constraints. We propose a heuristic based on weighted bipartite matching as a core routine. To improve its performance additional heuristics based on lookahead and segment splitting are also suggested. Experimental results are given to highlight the efficacy of track assignment stage in routing process.