Shortest paths in Euclidean graphs
Algorithmica
Fibonacci heaps and their uses in improved network optimization algorithms
Journal of the ACM (JACM)
Shortest paths algorithms: theory and experimental evaluation
Mathematical Programming: Series A and B
Undirected single-source shortest paths with positive integer weights in linear time
Journal of the ACM (JACM)
Single-source shortest-paths on arbitrary directed graphs in linear average-case time
SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
Using Multi-level Graphs for Timetable Information in Railway Systems
ALENEX '02 Revised Papers from the 4th International Workshop on Algorithm Engineering and Experiments
A Simple Shortest Path Algorithm with Linear Average Time
ESA '01 Proceedings of the 9th Annual European Symposium on Algorithms
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Computing the shortest path: A search meets graph theory
SODA '05 Proceedings of the sixteenth annual ACM-SIAM symposium on Discrete algorithms
Combining speed-up techniques for shortest-path computations
Journal of Experimental Algorithmics (JEA)
The Lee Path Connection Algorithm
IEEE Transactions on Computers
Speed-up techniques for shortest-path computations
STACS'07 Proceedings of the 24th annual conference on Theoretical aspects of computer science
Highway hierarchies hasten exact shortest path queries
ESA'05 Proceedings of the 13th annual European conference on Algorithms
Acceleration of shortest path and constrained shortest path computation
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
Partitioning graphs to speed up dijkstra's algorithm
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DUNE-a multilayer gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shortest path search using tiles and piecewise linear cost propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MARS-a multilevel full-chip gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms and data structures for fast and good VLSI routing
Proceedings of the 49th Annual Design Automation Conference
ACM Transactions on Interactive Intelligent Systems (TiiS) - Special issue on highlights of the decade in interactive intelligent systems
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We generalize Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices we label subgraphs which partition the given graph. We can achieve much better running times if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, our algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with a state-of-the-art routing tool on leading-edge industrial chips.