A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
Optimizing yield in global routing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing
Journal of Discrete Algorithms
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Gridless pin access in detailed routing
Proceedings of the 48th Design Automation Conference
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present advanced data structures and algorithms for fast and high-quality global and detailed routing in modern technologies. Global routing is based on a combinatorial approximation scheme for min-max resource sharing. Detailed routing uses exact shortest path algorithms, based on a shape-based data structure for pin access and a two-level track-based data structure for long-distance connections. All algorithms are very fast. We demonstrate their superiority over traditional approaches by a comparison to an industrial router (on 32nm and 22nm chips). Our router is over two times faster, has 5% less netlength, 20% less vias, and reduces detours by more than 90%.