Rectilinear paths among rectilinear obstacles
Discrete Applied Mathematics
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient escape routing for hexagonal array of high density I/Os
Proceedings of the 43rd annual Design Automation Conference
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
MARS-a multilevel full-chip gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms and data structures for fast and good VLSI routing
Proceedings of the 49th Annual Design Automation Conference
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rectilinear paths with minimum segment lengths
Discrete Applied Mathematics
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In the physical design of VLSI circuits, routing is one of the most important tasks. Usually done towards the end of the design process, especially the detailed routing phase has to obey virtually all design rules. As the feature size become ever smaller, shifts towards gridless design paradigms are necessary and a formerly trivial task, namely pin access, now becomes difficult. This work presents and discusses gridless pin access. In particular, we show how to create a feasible and efficient gridless routing approach that can be fit into existing gridded routing flows, creating a practical overall routing solution. As a key ingredient, our approach explicitly addresses design rule conform (shortest) paths among geometric obstacles, also taking violations within the paths themselves into consideration. Furthermore, redundancy exploiting structures called circuitclasses are introduced, and based on these, further improvements are described. We evaluated the approach on current gridless designs and present respective results: the routing performance is improved greatly both with respect to runtime and quality of the results.