Fast approximation algorithms for fractional packing and covering problems
Mathematics of Operations Research
Rectilinear paths among rectilinear obstacles
Discrete Applied Mathematics
Coordination complexity of parallel price-directive decomposition
Mathematics of Operations Research
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A sequential detailed router for huge grid graphs
Proceedings of the conference on Design, automation and test in Europe
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Net by Net Routing with a New Path Search Algorithm
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Sequential and Parallel Algorithms for Mixed Packing and Covering
FOCS '01 Proceedings of the 42nd IEEE symposium on Foundations of Computer Science
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Computing the shortest path: A search meets graph theory
SODA '05 Proceedings of the sixteenth annual ACM-SIAM symposium on Discrete algorithms
A DFM aware, space based router
Proceedings of the 2007 international symposium on Physical design
Optimizing yield in global routing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Faster and Simpler Algorithms for Multicommodity Flow and Other Fractional Packing Problems
SIAM Journal on Computing
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
Mathematical Programming: Series A and B
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing
Journal of Discrete Algorithms
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wire synthesizable global routing for timing closure
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
Gridless pin access in detailed routing
Proceedings of the 48th Design Automation Conference
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
A global router with a theoretical bound on the optimal solution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pseudopin assignment with crosstalk noise control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by new approximation algorithms for multicommodity flow
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Performance Routing at the Nanometer Scale
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MaizeRouter: Engineering an Effective Global Router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GRIP: Global Routing via Integer Programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present the core elements of BonnRoute: advanced data structures and algorithms for fast and high-quality routing in modern technologies. Global routing is based on a combinatorial approximation scheme for min-max resource sharing. Detailed routing uses exact shortest path algorithms, based on a shape-based data structure for pin access and a two-level track-based data structure for long-distance connections. All algorithms are very fast. Compared to an industrial router (on 32 nm and 22 nm chips), BonnRoute is over two times faster, has 5 % less netlength, 20 % less vias, and reduces detours by more than 90 %.