An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 45th annual Design Automation Conference
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Dummy fill optimization for enhanced manufacturability
Proceedings of the 19th international symposium on Physical design
Density gradient minimization with coupling-constrained dummy fill for CMP control
Proceedings of the 19th international symposium on Physical design
A gender-based genetic algorithm for the automatic configuration of algorithms
CP'09 Proceedings of the 15th international conference on Principles and practice of constraint programming
A parallel integer programming approach to global routing
Proceedings of the 47th Design Automation Conference
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
Congestion analysis for global routing via integer programming
Proceedings of the International Conference on Computer-Aided Design
New placement prediction and mitigation techniques for local routing congestion
Proceedings of the International Conference on Computer-Aided Design
Random search for hyper-parameter optimization
The Journal of Machine Learning Research
Algorithms and data structures for fast and good VLSI routing
Proceedings of the 49th Annual Design Automation Conference
GDRouter: interleaved global routing and detailed routing for ultimate routability
Proceedings of the 49th Annual Design Automation Conference
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MaizeRouter: Engineering an Effective Global Router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Taming the complexity of coordinated place and route
Proceedings of the 50th Annual Design Automation Conference
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Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast design closure can only be achieved by accurately evaluating whether a design is routable or not early in the design cycle. Lately, it has become common to use a “light mode” version of a global router to quickly evaluate the routability of a given placement. This approach suffers from three weaknesses: (i) it does not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing; (ii) the congestion maps obtained by it tend to have isolated hotspots surrounded by noncongested spots, called “noisy hotspots”, which further affects the accuracy in routability evaluation; and (iii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer, and moreover, they may often fail to predict the routability accurately. This article presents solutions to these issues. First, we propose three approaches to model local routing resources. Second, we propose a smoothing technique to reduce the number of noisy hotspots and obtain a more accurate routability evaluation result. Finally, we develop a new metric which represents congestion maps with higher fidelity. We apply the proposed techniques to several industrial circuits and demonstrate that one can better predict and evaluate design routability and that congestion mitigation tools can perform much better to improve the design routability.