Constraint graph-based macro placement for modern mixed-size circuit designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
Pulsed-latch aware placement for timing-integrity optimization
Proceedings of the 47th Design Automation Conference
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A parallel branch-and-cut approach for detailed placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
Unified analytical global placement for large-scale mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
A fast discrete placement algorithm for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A size scaling approach for mixed-size placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
A chip-package-board co-design methodology
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
Sub-quadratic objectives in quadratic placement
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient and effective analytical placer for FPGAs
Proceedings of the 50th Annual Design Automation Conference
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
VLSI legalization with minimum perturbation by iterative augmentation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
POLAR: placement based on novel rough legalization and refinement
Proceedings of the International Conference on Computer-Aided Design
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
Proceedings of the International Conference on Computer-Aided Design
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results.