One-processor scheduling with symmetric earliness and tardiness penalties
Mathematics of Operations Research
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
A faster strongly polynomial minimum cost flow algorithm
Operations Research
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Dragon2006: blockage-aware congestion-controlling mixed-size placer
Proceedings of the 2006 international symposium on Physical design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
Legalizing a placement with minimum total movement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Iterative placement improvement by network flow methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A network-flow based algorithm for power density mitigation at post-placement stage
Proceedings of the Conference on Design, Automation and Test in Europe
Sub-quadratic objectives in quadratic placement
Proceedings of the Conference on Design, Automation and Test in Europe
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
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We present a new approach to VLSI placement legalization. Based on a minimum-cost flow algorithm that iteratively augments flows along paths, our algorithm ensures that only augmentations are considered that can be realized exactly by cell movements. Hence, the method avoids realization problems which are inherent to previous flow-based legalization algorithms. As a result, it combines the global perspective of minimum-cost flow approaches with the efficiency of local search algorithms. The tool is mainly designed to minimize total and maximum cell movement but it is flexible enough to optimize the effect on timing or netlength, too. We compare our approach to legalization tools from industry and academia by experiments on dense recent real-world designs and public benchmarks. The results show that we are much faster and produce significantly better results in terms of average (linear and quadratic) and maximum movement than any other tool.