A multilevel analytical placement for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Proceedings of the 48th Design Automation Conference
VLSI legalization with minimum perturbation by iterative augmentation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Cell density-driven detailed placement with displacement constraint
Proceedings of the 2014 on International symposium on physical design
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
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Placement is one of the most important steps in the RTL-to-GDSII synthesis process as it directly defines the interconnects. The rapid increase in IC design complexity and the widespread use of intellectual-property blocks have made the so-called mixed-size placement a very important topic in recent years. The contributions of this paper include the following: 1) It proposes a flexible and robust mixed-size legalization scheme. Two constraint graphs are constructed from the global placement. Adjustments are iteratively applied to the constraint graphs until the longest paths on both graphs fall within the chip dimension. The macro coordinates are then computed by solving a linear programming (LP) formulation. The LP formulation has also been extended to handle macro spreading for routing density control. Experimental results show that our scheme can effectively legalize macros for all the global placements generated by mPL6 [1] on IBM-MSwPins. Experimental results also show that LP-based macro assignment can significantly reduce the amount of perturbation introduced during legalization compared to a greedy alternative. 2) Starting from the legalization scheme, it further proposes a three-step mixed-size detailed placement algorithm, XDP. An enhanced greedy method is used to remove the overlap between standard cells while preserving the legality of macros. Sliding-window-based cell swapping is applied in the end to further reduce the wirelength. Experiments show that, when compared with Floorist [2] with similar legalization capability, using the global placements generated by mPL6 [3], XDP is seven times faster with 6% shorter wirelength. Experiments also show that, when applied to the set of global placement results generated by APlace 2.0 [4], XDP can produce comparable wirelength to the native detailed placement of APlace 2.0 and 2% shorter wirelength compared with that with Fengshui 5.0 [5]. When applied to the set of global placements generated by mPL6, XDP is - - the only detailed placement that successfully produces legal placements for all 18 examples, whereas APlace and Fengshui failed for 3 and 16 of them, respectively. Furthermore, when legal placements can be compared, the wirelength produced by XDP is shorter by 8% on average compared with that with APlace. For scalability, XDP is ten times faster than APlace when applied to circuits with more than two million movable objects with comparable wirelength.