Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
ISPD 2006 Placement Contest: Benchmark Suite and Results
Proceedings of the 2006 international symposium on Physical design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Highly efficient gradient computation for density-constrained analytical placement methods
Proceedings of the 2008 international symposium on Physical design
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Modern Circuit Placement: Best Practices and Results
Modern Circuit Placement: Best Practices and Results
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Rethinking the wirelength benefit of 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
Proceedings of the 2014 on International symposium on physical design
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
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In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method [1], we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers.