Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs

Authors:
Shreepad Panth;Kambiz Samadi;Yang Du;Sung Kyu Lim
Affiliations:
Georgia Institute of Technology, Atlanta, GA, USA;Qualcomm Research, San Diego, CA, USA;Qualcomm Research, San Diego, CA, USA;Georgia Institute of Technology, Atlanta, GA, USA
Venue:
Proceedings of the 2014 on International symposium on physical design
Year:
2014

Citing 9
Cited 0

A linear-time heuristic for improving network partitions

DAC '82 Proceedings of the 19th Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation

ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A multilevel analytical placement for 3D ICs

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A study of Through-Silicon-Via impact on the 3D stacked IC layout

Proceedings of the 2009 International Conference on Computer-Aided Design
CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Proceedings of the 16th Asia and South Pacific Design Automation Conference
An effective congestion-driven placement framework

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power benefit study for ultra-high density transistor-level monolithic 3D ICs

Proceedings of the 50th Annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Monolithic 3D is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias (TSV). In this paper we demonstrate that a modified 2D placement technique, coupled with a post-placement partitioning step, is sufficient to produce high quality monolithic 3D placement solutions. We also present a commercial router based monolithic inter-tier via (MIV) insertion methodology that dramatically improves the routability of monolithic 3D-ICs. We develop a routing demand model for monolithic 3D-ICs, and use it to develop an O(N) min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product (PDP) by up to 4% and 4.33% respectively, under the same half-perimeter wirelength. This allows a two-tier monolithic 3D-IC to achieve, on average, 19.2% and 12.1% improvement in routed wirelength and PDP over 2D, even with reduced metal layer usage.