IBM Journal of Research and Development - POWER5 and packaging
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Thermal-Aware 3D IC Placement Via Transformation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
Proceedings of the 11th international workshop on System level interconnect prediction
Three-dimensional silicon integration
IBM Journal of Research and Development
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Homogeneous integration for 3D IC with TSV
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
An integrated algorithm for 3D-IC TSV assignment
Proceedings of the 48th Design Automation Conference
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Proceedings of the 48th Design Automation Conference
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
Proceedings of the 48th Design Automation Conference
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Proceedings of the International Conference on Computer-Aided Design
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs
Proceedings of the System Level Interconnect Prediction Workshop
Exploiting die-to-die thermal coupling in 3D IC placement
Proceedings of the 49th Annual Design Automation Conference
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Proceedings of the International Conference on Computer-Aided Design
Electromigration-aware routing for 3D ICs with stress-aware EM modeling
Proceedings of the International Conference on Computer-Aided Design
Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs
Proceedings of the International Conference on Computer-Aided Design
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs
Proceedings of the 50th Annual Design Automation Conference
Cell transformations and physical design techniques for 3D monolithic integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Communications of the ACM
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
Proceedings of the 2014 on International symposium on physical design
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
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Through-Silicon-Via (TSV) is the enabling technology for the fine-grained 3D integration of multiple dies into a single stack. These TSVs occupy non-negligible silicon area because of their sheer size. This significant silicon area occupied by the TSVs and the interconnections made to the TSVs greatly affect area, power, performance, and reliability of 3D IC layouts. Well-managed TSVs alleviate congestion, reduce wirelength, and improve performance, whereas excessive TSVs not only increase the die area, but also have negative impact on many design objectives. In this paper, we study the impact of TSV on various aspects of 3D layouts. We use GDSII layouts of 2D and 3D designs, and thoroughly compare the pros and cons of TSV usage. We propose a new force-directed 3D gate-level placement that efficiently handles TSVs. In addition, we present an algorithm that assigns TSVs to nets to complete routing that involves TSVs. This algorithm, together with our 3D placer, is integrated into a commercial P&R tool to generate fully validated GDSII layouts. Our experiments based on synthesized benchmarks indicate that our algorithms help generate GDSII layouts of 3D designs that are optimized in terms of area, wirelength, and metal layer count.