Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Case Study of a 65-nm SoC Design
IEEE Design & Test
Reducing the leakage and timing variability of 2D ICs using 3D ICs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Wafer-level 3D integration technology
IBM Journal of Research and Development
Through-silicon vias enable next-generation SiGe power amplifiers forwireless communications
IBM Journal of Research and Development
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
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3D IC integration is very important to overcome the technology scaling barriers and to satisfy mobile devices' demand. In this paper, we describe the challenges we are facing in developing 3D IC design methodology, especially in the case of TSV-SiP (Logic-Memory die stacking). Also, appropriate development approaches are proposed. The EDA tools for TSV-SiP, which are initially provided by extending current conventional tools, will be gradually enhanced to better support 3D IC designs.