Power-Constrained Microprocessor Design
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Physical Design for 3D System on Package
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimal topology exploration for application-specific 3D architectures
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Ultralow-voltage, minimum-energy CMOS
IBM Journal of Research and Development - Advanced silicon technology
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
A multi-story power delivery technique for 3D integrated circuits
Proceedings of the 13th international symposium on Low power electronics and design
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
Thermomechanical modeling of 3D electronic packages
IBM Journal of Research and Development
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Analysis of photonic networks for a chip multiprocessor using scientific applications
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
An analytical placer for mixed-size 3D placement
Proceedings of the 19th international symposium on Physical design
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Proceedings of the 37th annual international symposium on Computer architecture
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Homogeneous integration for 3D IC with TSV
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
OPAL: a multi-layer hybrid photonic NoC for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Journal of Electronic Testing: Theory and Applications
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Integration, the VLSI Journal
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Despite generation upon generation of scaling, computer chips have until now remained essentially 2-dimensional. Improvements in on-chip wire delay and in the maximum number of I/O per chip have not been able to keep up with transistor performance growth; it has become steadily harder to hide the discrepancy. 3D chip technologies come in a number of flavors, but are expected to enable the extension of CMOS performance. Designing in three dimensions, however, forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities.