Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Optimal partitioners and end-case placers for standard-cell layout
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Hypergraph-Partitioning-Based Decomposition for Parallel Sparse-Matrix Vector Multiplication
IEEE Transactions on Parallel and Distributed Systems
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Reporting of standard cell placement results
Proceedings of the 2001 international symposium on Physical design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '84 Proceedings of the 21st Design Automation Conference
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Physical Design for 3D System on Package
IEEE Design & Test
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wire congestion and thermal aware 3D global placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
A multi-story power delivery technique for 3D integrated circuits
Proceedings of the 13th international symposium on Low power electronics and design
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach
Integration, the VLSI Journal
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A low power 3D integrated FFT engine using hypercube memory division
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study
Proceedings of the 46th Annual Design Automation Conference
Performance and thermal-aware Steiner routing for 3-D stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wirelength-driven force-directed 3D FPGA placement
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
CAD reference flow for 3D via-last integrated circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Multi-objective module placement for 3-d system-on-package
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for architecture-level exploration of 3-D FPGA platforms
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Cell transformations and physical design techniques for 3D monolithic integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A novel 3-D FPGA architecture targeting communication intensive applications
Journal of Systems Architecture: the EUROMICRO Journal
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We present a set of design tools for 3-D Integration. Using these tools - a 3-D standard-cell placement tool, global routing tool, and layout editor - we have targeted existing standard-cell circuit netlists for fabrication using wafer bonding. We have analyzed the performance of several circuits using these tools and find that 3-D integration provides significant benefits. For example, relative to single-die placement, we observe on average 28% to 51% reduction in total wire length.