A vertically integrated VLSI design environment
DAC '83 Proceedings of the 20th Design Automation Conference
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Plowing: Interactive stretching and compaction in magic
DAC '84 Proceedings of the 21st Design Automation Conference
A switchbox router with obstacle avoidance
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
DAC '82 Proceedings of the 19th Design Automation Conference
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
The User Interface and Implementation of Caesar
The User Interface and Implementation of Caesar
PAMS: an expert system for parameterized module synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Gray Codes for Partial Match and Range Queries
IEEE Transactions on Software Engineering
Fractals for secondary key retrieval
PODS '89 Proceedings of the eighth ACM SIGACT-SIGMOD-SIGART symposium on Principles of database systems
Fast online/offline netlist compilation of hierarchical schematics
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Linking programs incrementally
ACM Transactions on Programming Languages and Systems (TOPLAS)
A practical online design rule checking system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
SIGMOD '92 Proceedings of the 1992 ACM SIGMOD international conference on Management of data
A categorized bibliography on incremental computation
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
OPERAS in a DSP CAD environment
EURO-DAC '94 Proceedings of the conference on European design automation
Deriving efficient area and delay estimates by modeling layout tools
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient decomposition of polygons into L-shapes with application to VLSI layouts
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A notation for describing multiple views of VLSI circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
An efficient compactor for 45° layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The edge-based design rule model revisited
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comparison of scalable superscalar processors
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SMR-tree: an efficient index structure for spatial databases
SAC '95 Proceedings of the 1995 ACM symposium on Applied computing
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Layout design—lessons from the Jedi designer (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
PLA driver selection: an analytic approach
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
GENERIC: a silicon compiler support language
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MADMACS: a new VLSI layout macro editor
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Dual quadtree representation for VLSI designs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Using texture mapping with mipmapping to render a VLSI layout
Proceedings of the 38th annual Design Automation Conference
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Hierarchical VLSI design systems based on attribute grammars
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The R+-Tree: A Dynamic Index for Multi-Dimensional Objects
VLDB '87 Proceedings of the 13th International Conference on Very Large Data Bases
Hilbert R-tree: An Improved R-tree using Fractals
VLDB '94 Proceedings of the 20th International Conference on Very Large Data Bases
The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Plowing: Interactive stretching and compaction in magic
DAC '84 Proceedings of the 21st Design Automation Conference
A switchbox router with obstacle avoidance
DAC '84 Proceedings of the 21st Design Automation Conference
Architecture of SOAR: Smalltalk on a RISC
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A data-structuring technique for gridded VLSI layouts
EURO-DAC '90 Proceedings of the conference on European design automation
MOLE: a sea-of-gates detailed router
EURO-DAC '90 Proceedings of the conference on European design automation
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 32nd annual international symposium on Computer Architecture
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Utility of the OpenAccess database in academic research
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An efficient algorithm for partitioning parameterized polygons into rectangles
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems
Journal of VLSI Signal Processing Systems
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Self-tuning management of update-intensive multidimensional data in clusters of workstations
The VLDB Journal — The International Journal on Very Large Data Bases
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Low-power FinFET circuit synthesis using surface orientation optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Fault simulation and test pattern generation at the multiple-valued switch level
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Magic is a “smart” layout system for integrated circuits. The user interface is based on a new design style called logs, which combines the efficiency of mask-level design with the flexibility of symbolic design. The system incorporates expertise about design rules and connectivity directly into the layout system in order to implement powerful new operations, including: a continuous design-rule checker that operates in background to maintain an up-to-date picture of violations; an operation called plowing that permits interactive stretching and compaction; and routing tools that can work under and around existing connections in the channels. Magic uses a new data structure called corner stitching to achieve an efficient implementation of these operations.