A notation for describing multiple views of VLSI circuits

Authors:
Jean-Loup Baer;Meei-Chiueh Liem;Larry McMurchie;Rudolf Nottrott;Lawrence Snyder;Wayne Winder
Affiliations:
NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA;NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA;NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA;NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA;NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA;NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

Citing 5
Cited 1

Hierarchical design based on a calculus of nets

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A design by example regular structure generator

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
MOS circuit models in Network C

DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Zeus: A hardware description language for VLSI

DAC '83 Proceedings of the 20th Design Automation Conference
Magic: A VLSI layout system

DAC '84 Proceedings of the 21st Design Automation Conference

NAUTILE: a safe environment for silicon compilation

EURO-DAC '90 Proceedings of the conference on European design automation

Quantified Score

Hi-index	0.00

Visualization

Abstract

A declarative hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basis of a structured environment for developing design generators as well as capturing design expertise.