CLU reference manual
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to VLSI Systems
GRASP: a grammar-based schematic parser
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Hierarchical pitchmatching compaction using minimum design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Cell-based hierarchical pitchmatching compaction using minimal LP
DAC '93 Proceedings of the 30th international Design Automation Conference
A notation for describing multiple views of VLSI circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HIMALAYAS — a hierarchical compaction system with a minimized constraint set
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
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This paper investigates technical issues concerning the automated generation of highly regular VLSI circuit layouts (e.g. RAMs, PLAs, systolic arrays) that are crucial to the designability and realizability of large VLSI systems. The key is to determine the most profitable level of abstraction for the designer, which is accomplished by the introduction of macro abstraction, interface inheritance, delayed binding, and the complete decoupling of procedural and graphical design information. These abstraction mechanisms are implemented in the Regular Structure Generator, an operational layout generator with significant advantages over first generation layout tools. Its advantages are demonstrated by a pipelined array multiplier layout example.