A data-structuring technique for gridded VLSI layouts

Authors:
Saleem M. Haider;Peng H. Ang
Affiliations:
Western Software Lab, Digital Equipment Corp., Palo Alto, CA;Systems Research Lab, LSI Logic Corp., Menlo Park, CA
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

Citing 3
Cited 0

Data Structures for Range Searching

ACM Computing Surveys (CSUR)
Magic: A VLSI layout system

DAC '84 Proceedings of the 21st Design Automation Conference
The quad-CIF tree: A data structure for hierarchical on-line algorithms

DAC '82 Proceedings of the 19th Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the LINKED ARRAY data structure for storing rectangular structures which are constrained to a grid. The data structure is particularly useful in integrated layout systems for VLSI technologies like gate-arrays; it is also useful for building schematic editors. This data structure has been used to implement a prototype layout system which has significant memory usage and timing response advantages for large layouts (~ 100,000 used gates, running on a workstation like SUN 3/260). The paper describes how the data structure is created, how it operates, and how it compares with existing mechanisms.