Introduction to algorithms
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Efficient decomposition of polygons into L-shapes with application to VLSI layouts
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Layout-oriented synthesis of high performance analog circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Introduction to VLSI Systems
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '84 Proceedings of the 21st Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference
An efficient algorithm for partitioning parameterized polygons into rectangles
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Computational Geometry: Algorithms and Applications
Computational Geometry: Algorithms and Applications
Corner stitching for simple rectilinear shapes [VLSI layouts]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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An algorithm for partitioning parameterized 45-degree polygons into parameterized trapezoids is proposed in this article. The algorithm is based on the plane-sweep technique and can handle polygons with complicated constraints. The input to the algorithm consists of the contour of a parameterized polygon to be partitioned and a set of constraints for parameters of the contour. The algorithm uses horizontal cuts only and generates a number of nonoverlapping trapezoids whose union is the original parameterized polygon. Processing of constraints and coordinates that contain first-order multiple-variable polynomials has been made possible by incorporating the JaCoP constraint programming library. The proposed algorithm has been implemented in Java programming language and can be used as the basis to build the trapezoidal corner stitching data structure for parameterized VLSI layout masks.