Efficient decomposition of polygons into L-shapes with application to VLSI layouts
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computational geometry: algorithms and applications
Computational geometry: algorithms and applications
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Accurate Estimation of Parasitic Capacitances in Analog Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing query processing in cache-aware wireless sensor networks
SSDBM'10 Proceedings of the 22nd international conference on Scientific and statistical database management
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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In this paper, we propose an algorithm for partitioning parameterized orthogonal polygons into rectangles. The algorithm is based on the plane-sweep technique and can be used for partitioning polygons which contain holes. The input to the algorithm consists of the contour of a parameterized polygon to be partitioned and the constraints for those parameters which reside in the contour. The algorithm uses horizontal cuts only and generates a minimum number of rectangles whose union is the original orthogonal polygon. The proposed algorithm can be used as the basis to build corner stitching data structure for parameterized VLSI layouts and has been implemented in Java programming language.