A sweepline algorithm for Voronoi diagrams
SCG '86 Proceedings of the second annual symposium on Computational geometry
Computational geometry: algorithms and applications
Computational geometry: algorithms and applications
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
An interactive router for analog IC design
Proceedings of the conference on Design, automation and test in Europe
DAC '84 Proceedings of the 21st Design Automation Conference
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Plowing: Interactive stretching and compaction in magic
DAC '84 Proceedings of the 21st Design Automation Conference
A switchbox router with obstacle avoidance
DAC '84 Proceedings of the 21st Design Automation Conference
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
An efficient algorithm for partitioning parameterized polygons into rectangles
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Algorithms for Reporting and Counting Geometric Intersections
IEEE Transactions on Computers
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using OpenMP: Portable Shared Memory Parallel Programming (Scientific and Engineering Computation)
Using OpenMP: Portable Shared Memory Parallel Programming (Scientific and Engineering Computation)
A Polygon-to-Rectangle Conversion Algorithm
IEEE Computer Graphics and Applications
Introduction to Algorithms, Third Edition
Introduction to Algorithms, Third Edition
A parallel plane sweep algorithm for multi-core systems
Proceedings of the 17th ACM SIGSPATIAL International Conference on Advances in Geographic Information Systems
CMOS Circuit Design, Layout, and Simulation
CMOS Circuit Design, Layout, and Simulation
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
Tailor: a layout system based on trapezoidal corner stitching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast algorithm for polygon decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In order to use rectangular corner stitching data structures in storing parameterized orthogonal layouts, parameterized polygons in the layouts must be partitioned into rectangles. Likewise, in order to use trapezoidal corner stitching data structures in storing parameterized 45-degree layouts, parameterized polygons in the layouts have to be partitioned into trapezoids. In this article, a parallel polygon partitioning algorithm is proposed; the algorithm is capable of partitioning parameterized orthogonal polygons into parameterized rectangles as well as partitioning parameterized 45-degree polygons into parameterized trapezoids. Additionally, the algorithm can be used to partition fixed-coordinate polygons. By adopting the dual-scanline technique, which involves using two scanlines to concurrently sweep an input polygon, the parallel partitioning algorithm can process vertices and edges of the input polygon efficiently. The parallel polygon partitioning algorithm has been implemented in C++ with the use of OpenMP. Compared with a sequential partitioning program which uses a single scanline, our parallel partitioning program can achieve 20% to 30% speedup while partitioning large parameterized polygons or partitioning parameterized polygons with complex constraints.