A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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A VLSI layout design system named Tailor is described. Tailor operates on hierarchical layouts containing 45° multiple angles. It consists of a well-integrated set of tools, including a window-driven editor, an incremental design rule checker, a circuit extractor, a one-dimensional compactor, a channel-based global router, and a transistor size optimizer. All tools use the same user interface and operate directly on Tailor's trapezoidal corner stitched database. Tailor's database structure is well suited for all of the tools because all important database operations, such as point searching, neighbor searching, area searching, and shadow searching, function very efficiently. All the tools in Tailor, except transistor optimization and routing, work directly on the layout hierarchy, which provides even greater efficiency