Magic's incremental design-rule checker

Authors:
George S. Taylor;John K. Ousterhout
Affiliations:
Computer Science Division, Electrical Engineering and Computer Sciences Department, University of California, Berkeley, California;Computer Science Division, Electrical Engineering and Computer Sciences Department, University of California, Berkeley, California
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

Citing 2
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Abstract

The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs.