Introduction to VLSI Systems
An O(nlogm) algorithm for VLSI design rule checking
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The use of inverse layout trees for hierarchical design rule checking
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The edge-based design rule model revisited
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An algorithm for design rule checking on a multiprocessor
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Dual quadtree representation for VLSI designs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
Hierarchical layout verification
DAC '84 Proceedings of the 21st Design Automation Conference
VLSI tools and architectures: Putting the new technology to work
CSC-83 Proceedings of the 1983 computer science conference
Incremental analysis of large VLSI Layouts
Integration, the VLSI Journal
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Lyra is a layout rule checking program for Manhattan VLSI circuits. In Lyra, rules are specified in terms of constraints that must hold at certain corners in the design. The corner-based mechanism permits a wide variety of rules to be specified easily, including rules involving asymmetric constructs such as transistor overhangs. Lyra's mechanism also has locality, which can be exploited to construct incremental and/or hierarchical checkers. A rule compiler translates symbolic rules into efficient code for checking those rules, and permits the system to be retargeted for different processes.