The input/output complexity of sorting and related problems
Communications of the ACM
An O(nlogm) algorithm for VLSI design rule checking
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient memory access in large-scale computation (invited paper)
STACS 91 Proceedings of the 8th annual symposium on Theoretical aspects of computer science
Efficient algorithms for counting and reporting pairwise intersections between convex polygons
Information Processing Letters
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A time and space efficient net extractor
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
External memory algorithms and data structures: dealing with massive data
ACM Computing Surveys (CSUR)
Introduction to VLSI Systems
The Buffer Tree: A New Technique for Optimal I/O-Algorithms (Extended Abstract)
WADS '95 Proceedings of the 4th International Workshop on Algorithms and Data Structures
DAC '83 Proceedings of the 20th Design Automation Conference
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
EXCL: A circuit extractor for IC designs
DAC '84 Proceedings of the 21st Design Automation Conference
A hardware assisted design rule check architecture
DAC '82 Proceedings of the 19th Design Automation Conference
Lyra: A new approach to geometric layout rule checking
DAC '82 Proceedings of the 19th Design Automation Conference
An Efficient External-Memory Implementation of Region Query with Application to Area Routing
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
An External Memory Circuit Validation Algorithm for Large VLSI Layouts
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Geometric intersection problems
SFCS '76 Proceedings of the 17th Annual Symposium on Foundations of Computer Science
Efficient net extraction for restricted orientation designs [VLSI layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Time-efficient VLSI artwork analysis algorithms in GOALIE2
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal definitions of edge-based geometric design rules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A space-efficient short-finding algorithm [VLSI layouts]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The verification of VLSI layouts is an important and expensive step in physical design process and has significant contribution in overall design cycle time. Design rule checking, connectivity extraction and device extraction are important steps in layout analysis. Efficient incremental algorithms for these steps are crucial for fast development as well as small time-to-market of the design. If the size of layout is so large that it cannot fit entirely into available main memory, the main performance bottleneck is communication between internal memory and the external memory due to the slow access speed of external memory. In this paper, incremental solutions for problems of layout analysis are presented considering the external memory management. The main component of these algorithms is the proposed ''recursive tiling'' approach, which provides an easy to implement data structure for the aggregation of parts of layout for fast search and updates. Experimental results show that the recursive tiling approach proposed in this paper has reduced the time required for incremental processing on the workstations with limited amount of physical memory.