Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
DAC '83 Proceedings of the 20th Design Automation Conference
PANAMAP-B: A mask verification system for bipolar IC
DAC '81 Proceedings of the 18th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
RED: resistance extraction for digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An efficient finite element method for submicron IC capacitance extraction
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delayed frontal solution for finite-element based resistance extraction
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Using articulation nodes to improve the efficiency of finite-element based resistance extraction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Analyzing CMOS power supply networks using Ariel
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Recent results in VLSI CAD at MIT
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Incremental analysis of large VLSI Layouts
Integration, the VLSI Journal
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This paper describes EXCL, an automated circuit extraction program that transforms an IC layout into a circuit representation suitable for detailed circuit simulation. The program has built-in, general extraction algorithms capable of accurate computations of interconnection resistance, internodal capacitance, ground capacitance, and transistor sizes. However, where possible, the general algorithms are replaced with simple techniques, thereby improving execution speed. A basic component of the extractor is a procedure that decomposes regions into domains appropriate for specialized or simple algorithms. The paper describes the decomposition algorithm, the extraction algorithms and discusses how they connect with the rest of EXCL.