Symbolic Parasitic Extractor for Circuit Simulation (SPECS)

  • Authors:

  • J. D. Bastian;M. Ellement;P. J. Fowler;C. E. Huang;L. P. McNamee

  • Affiliations:

  • Rockwell International Corporation, Defense Electronics Operations, Microelectronics Research & Development, 3370 Miraloma Avenue, Anaheim, California;Computer Science Department, University of California at Los Angeles;Rockwell International Corporation, Defense Electronics Operations, Microelectronics Research & Development, 3370 Miraloma Avenue, Anaheim, California;Computer Science Department, University of California at Los Angeles;Computer Science Department, University of California at Los Angeles

  • Venue:
  • DAC '83 Proceedings of the 20th Design Automation Conference
  • Year:
  • 1983

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Abstract

This paper describes the design, development and implementation of the program SPECS. The purpose of SPECS is to automatically extract from a Rockwell microelectronic symbolic matrix description a netlist for circuit simulation. This program differs from others in that it uses a symbol layout matrix as an input, calculates both interelectrode and intrinsic capacitance, calculates conductor resistance, produces a schematic representation of the network and has a selective TRACE, i.e., traces only the circuit or network of interest.