Design rule checking and analysis of IC mask designs
DAC '76 Proceedings of the 13th Design Automation Conference
Computer aided LSI circuit design: A relationship between topology and performance
DAC '75 Proceedings of the 12th Design Automation Conference
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
25 years of DAC Papers on Twenty-five years of electronic design automation
An O (N log N) algorithm for boolean mask operations
25 years of DAC Papers on Twenty-five years of electronic design automation
Hcompare: a hierarchical netlist comparison program
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ACM SIGDA Newsletter
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
DAC '83 Proceedings of the 20th Design Automation Conference
Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Efficient Boolean operations on IC masks
DAC '81 Proceedings of the 18th Design Automation Conference
PANAMAP-B: A mask verification system for bipolar IC
DAC '81 Proceedings of the 18th Design Automation Conference
Design integrity and immunity checking: A new look at layout verification and design rule checking
DAC '80 Proceedings of the 17th Design Automation Conference
A hierarchical approach for layout versus circuit consistency check
DAC '80 Proceedings of the 17th Design Automation Conference
An integrated mask artwork analysis system
DAC '80 Proceedings of the 17th Design Automation Conference
Programs for verifying circuit connectivity of mos/lsi mask artwork
DAC '82 Proceedings of the 19th Design Automation Conference
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
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Algorithms are presented which use a bit map approach to derive connectivity checks, design rule checks, and electrical parameters for VLSI circuit artwork.