A computer-aided VLSI layout system

Authors:
W. A. Dees;K. M. Parmar;A. Goyal;R. Y. Tsui;B. D. Rathi;R. J. Smith, II
Affiliations:
University of Texas at Austin, Austin, Texas;University of Texas at Austin, Austin, Texas;University of Texas at Austin, Austin, Texas;University of Texas at Austin, Austin, Texas;University of Texas at Austin, Austin, Texas;University of Texas at Austin, Austin, Texas
Venue:
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Year:
1981

Citing 15
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Abstract

The VLSI layout system is suggested as a practical approach for solving large and complex problems introduced by today's VLSI technology. Computer-based design aids are introduced which are utilized to effectively reduce design time and to increase product quality. A hierarchical description of VLSI circuits is utilized to partition the problem into manageable tasks. Each phase of the VLSI chip design cycle is discussed with special emphasis on layout techniques. The hierarchical VLSI layout system is applicable to the design of "semicustom" or master-slice VLSI circuits. The placement and placement optimization portions of the proposed system have been implemented. Routing and routing optimization techniques are currently being developed.