Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
On the optimum two-dimensional allocation problem
DAC '78 Proceedings of the 15th Design Automation Conference
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
DAC '76 Proceedings of the 13th Design Automation Conference
An hierarchical language for the structural description of digital systems
DAC '77 Proceedings of the 14th Design Automation Conference
Placement and routing algorithms for hierarchical integrated circuit layout
Placement and routing algorithms for hierarchical integrated circuit layout
Efficient floorplan area optimization
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Cooperative approach to a practical analog LSI layout system
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HAPPI: a chip compiler based on double-level-metal technology
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Rectilinear block placement using B*-trees
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement algorithms for custom VLSI
DAC '83 Proceedings of the 20th Design Automation Conference
Computation of power supply nets in VLSI layout
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic component placement in an interactive minicomputer environment
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic placement of rectangular blocks with the interconnection channels
DAC '81 Proceedings of the 18th Design Automation Conference
A dogleg “optimal” channel router with completion enhancements
DAC '81 Proceedings of the 18th Design Automation Conference
Cell map representation for hierarchical layout
DAC '80 Proceedings of the 17th Design Automation Conference
An analytical method for compacting routing area in integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
On finding most optimal rectangular package plans
DAC '82 Proceedings of the 19th Design Automation Conference
Rectilinear Block Placement Using B*-Trees
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Optimal slicing of plane point placements
EURO-DAC '90 Proceedings of the conference on European design automation
Relative placement representation
ACM SIGDA Newsletter
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Placement algorithms for custom VLSI
Computer-Aided Design
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constraint-aware interior layout exploration for pre-cast concrete-based buildings
The Visual Computer: International Journal of Computer Graphics
From design to design automation
Proceedings of the 2014 on International symposium on physical design
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New placement algorithms have been developed which are suitable for the layout of Very Large Scale Integrated (VLSI) circuits Hierarchical decomposition is used to reduce the circuit function to a size that can be comprehended by the designer and is computationally feasible to layout. At each hierarchical level the problem consists of the placement of interconnected rectangular blocks of arbitrary size and shape such that the area occupied by the blocks and their interconnections is minimal. Constructive initial placement and iterative improvement algorithms are presented.