An optimum layer assignment for routing in ICs and PCBs.
DAC '81 Proceedings of the 18th Design Automation Conference
Cell map representation for hierarchical layout
DAC '80 Proceedings of the 17th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
DAC '79 Proceedings of the 16th Design Automation Conference
Placement algorithms for arbitrarily shaped blocks
DAC '79 Proceedings of the 16th Design Automation Conference
Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
Block placement to ensure channel routability
Proceedings of the 17th ACM Great Lakes symposium on VLSI
| Hi-index | 0.00 |
An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed.