Automated printed circuit routing with a stepping aperture
Communications of the ACM
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
Cellular wiring and the cellular modeling technique
DAC '69 Proceedings of the 6th annual Design Automation Conference
Routing multiterminal nets around a rectangle
IEEE Transactions on Computers - The MIT Press scientific computation series
Optimal Rotation Problems in Channel Routing
IEEE Transactions on Computers
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Abstract routing of logic networks for custom module generation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Automated layout generation using gate matrix approach
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Routing with a scanning window-8Ma unified approach
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layer Assignment Problem for Three-Layer Routing
IEEE Transactions on Computers
A linear time algorithm for optimal routing around a rectangle
Journal of the ACM (JACM)
An expert system for channel routing
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 2
An optimum channel-routing algorithm for polycell layouts of integrated circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
The chip layout problem: an automatic wiring procedure
25 years of DAC Papers on Twenty-five years of electronic design automation
A multi-pass, multi-algorithm approach to PCB routing
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
Optimal Three-Layer Channel Routing
IEEE Transactions on Computers
The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The Via Minimization Problem is NP-Complete
IEEE Transactions on Computers
Pad placement and ring routing for custom chip layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An Efficient Channel Routing Algorithm to Yield an Optimal Solution
IEEE Transactions on Computers
PALACE: a layout generator for SCVS logic blocks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
MISER: an integrated three layer gridless channel router and compactor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Channel density reduction by routing over the cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Flexible transistor matrix (FTM)
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient layout style for 2-metal CMOS leaf cells and their automatic generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A pin permutation algorithm for improving over-the-cell channel routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Channel-driven global routing with consistent placement (extended abstract)
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Routing in a new 2-dimensional FPGA/FPIC routing architecture
DAC '94 Proceedings of the 31st annual Design Automation Conference
Nearly optimal algorithms and bounds for multilayer channel routing
Journal of the ACM (JACM)
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Fast algorithm for optimal layer assignment
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The constrained via minimization problem for PCB and VLSI design
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Improved channel routing by via minimization and shifting
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A performance-driven layer assignment algorithm for multiple interconnect trees
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A graph-partitioning-based approach for multi-layer constrained via minimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
New channel segmentation model and associated routing algorithm for high performance FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
MOSAIC: a tile-based datapath layout generator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
NP-completeness of the domatic number problem on circular arc graphs
ACM-SE 37 Proceedings of the 37th annual Southeast regional conference (CD-ROM)
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic routing algorithm for VLSI
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Chameleon: a new multi-layer channel router
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A preprocessor for the via minimization problem
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Router system for printed wiring boards of very high-speed, very large-scale computers
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
On the equivalence of pull-up transistor assignment in PLA folding and distribution graph
SAC '94 Proceedings of the 1994 ACM symposium on Applied computing
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Noise-aware power optimization for on-chip interconnect
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Three-layer bubble-sorting-based nonManhattan channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An exact algorithm for solving difficult detailed routing problems
Proceedings of the 2001 international symposium on Physical design
A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
Comparative router performance
ACM SIGDA Newsletter
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the area of hypercube layouts
Information Processing Letters
Performance Driven Routing in Distributed Environment
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
3-Dimensional Single Active Layer Routing
JCDCG '00 Revised Papers from the Japanese Conference on Discrete and Computational Geometry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routing method for VLSI design using irregular cells
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
A topology for semicustom array-structured LSI devices, and their automatic customisation
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Cell compilation with constraints
DAC '84 Proceedings of the 21st Design Automation Conference
GALA - an automatic layout system for high density CMOS gate arrays
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
Performance of interconnection rip-up and reroute strategies
DAC '81 Proceedings of the 18th Design Automation Conference
Aiming at a general routing strategy
DAC '81 Proceedings of the 18th Design Automation Conference
An optimum layer assignment for routing in ICs and PCBs.
DAC '81 Proceedings of the 18th Design Automation Conference
A dogleg “optimal” channel router with completion enhancements
DAC '81 Proceedings of the 18th Design Automation Conference
SHARPS: A hierarchical layout system for VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Implementation of an interactive printed circuit design system
DAC '78 Proceedings of the 15th Design Automation Conference
A multi-pass, multi-algorithm approach to PCB routing
DAC '78 Proceedings of the 15th Design Automation Conference
A topologically based non-minimum distance routing algorithm
DAC '78 Proceedings of the 15th Design Automation Conference
The interconnection problem - a tutorial
DAC '73 Proceedings of the 10th Design Automation Workshop
An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
GRAFOS - A symbolic routing language
DAC '73 Proceedings of the 10th Design Automation Workshop
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
A layout system for the random logic portion of MOS LSI
DAC '80 Proceedings of the 17th Design Automation Conference
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
An automatic routing system for high density multilayer printed wiring boards
DAC '80 Proceedings of the 17th Design Automation Conference
A data structure for gridless routing
DAC '80 Proceedings of the 17th Design Automation Conference
A new routing algorithm for two-sided boards with floating vias
DAC '76 Proceedings of the 13th Design Automation Conference
Automatic generation of logic diagrams
DAC '76 Proceedings of the 13th Design Automation Conference
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
On the topological aspects of the circuit layout problem
DAC '76 Proceedings of the 13th Design Automation Conference
Topologic class routing for printed circuit boards
DAC '72 Proceedings of the 9th Design Automation Workshop
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
An approximation algorithm for manhattan routing
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A heuristic procedure for ordering MOS arrays
DAC '75 Proceedings of the 12th Design Automation Conference
Floss: An approach to automated layout for high-volume designs
DAC '77 Proceedings of the 14th Design Automation Conference
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
An analytical method for compacting routing area in integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
A minimum-impact routing algorithm
DAC '82 Proceedings of the 19th Design Automation Conference
The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers
DAC '82 Proceedings of the 19th Design Automation Conference
A consideration of the number of horizontal grids used in the routing of a masterslice layout
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Automated rip-up and reroute techniques
DAC '82 Proceedings of the 19th Design Automation Conference
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
Two-dimensional channel routing and channel intersection problems
DAC '82 Proceedings of the 19th Design Automation Conference
Hierarchical top-down layout design method for VLSI chip
DAC '82 Proceedings of the 19th Design Automation Conference
CGALA-a multi technology Gate Array Layout system
DAC '82 Proceedings of the 19th Design Automation Conference
On routing two-point nets across a channel
DAC '82 Proceedings of the 19th Design Automation Conference
A hierarchical placement procedure with a simple blocking scheme
DAC '79 Proceedings of the 16th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
The minimum width routing of A 2-row 2-layer polycell-layout
DAC '79 Proceedings of the 16th Design Automation Conference
A general graph theoretic framework for multi-layer channel routing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Computing area and wire length efficient routes for channels
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
PARAGON: a new package for gate matrix layout synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
Module synthesis for finite state machines
EURO-DAC '91 Proceedings of the conference on European design automation
A multiple-population evolutionary approach to gate matrix layout
International Journal of Systems Science
An interactive system for VLSI chip physical design
IBM Journal of Research and Development
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
QCA channel routing with wire crossing minimization
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Optimising automatic tracking of multilayer boards
ACM SIGDA Newsletter
ACM SIGDA Newsletter
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
The effect of machine availability on the worst-case performance of LPT
Discrete Applied Mathematics
Effective techniques for the generalized low-power binding problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Multilevel routing with jumper insertion for antenna avoidance
Integration, the VLSI Journal
Conjugate conflict continuation graphs for multi-layer constrained via minimization
Information Sciences: an International Journal
Routing vertex disjoint steiner-trees in a cubic grid and connections to VLSI
Discrete Applied Mathematics
A Near-Optimal Parallel Algorithm for One-Dimensional Gate Assignment in VLSI Layout
Integrated Computer-Aided Engineering
Escape routing for dense pin clusters in integrated circuits
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computers
A Wire-Routing Scheme Based on Trunk-Division Methods
IEEE Transactions on Computers
A Wire-Routing Scheme Based on Trunk-Division Methods
IEEE Transactions on Computers
A Layout System for the Random Logic Portion of an MOS LSI Chip
IEEE Transactions on Computers
Optimal Wiring of Movable Terminals
IEEE Transactions on Computers
On the Ordering of Connections for Automatic Wire Routing
IEEE Transactions on Computers
Computation of storage requirements for multi-dimensional signal processing applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Integrated Computer-Aided Engineering
Power-gating-aware high-level synthesis
Proceedings of the 13th international symposium on Low power electronics and design
Journal of Signal Processing Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
Integration, the VLSI Journal
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Influence on LSI package wireability of via availability and wiring track accessibility
IBM Journal of Research and Development
Pad assignment for die-stacking System-in-Package design
Proceedings of the 2009 International Conference on Computer-Aided Design
The effect of machine availability on the worst-case performance of LPT
Discrete Applied Mathematics
Algorithms for permutation channel routing
Integration, the VLSI Journal
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Algorithms and theory of computation handbook
On the 2-Dimensional Channel Assignment Problem
IEEE Transactions on Computers
High-level synthesis for designing multimode architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
RegularRoute: an efficient detailed router with regular routing patterns
Proceedings of the 2011 international symposium on Physical design
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Solving VLSI design and DNA sequencing problems using bipartization of graphs
Computational Optimization and Applications
Density-reduction-oriented layer assignment for rectangle escape routing
Proceedings of the great lakes symposium on VLSI
New optimal layer assignment for bus-oriented escape routing
Integration, the VLSI Journal
Dawn of computer-aided design: from graph-theory to place and route
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.