Theory of linear and integer programming
Theory of linear and integer programming
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A data locality optimizing algorithm
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
A practical algorithm for exact array dependence analysis
Communications of the ACM
A singular value decomposition updating algorithm for subspace tracking
SIAM Journal on Matrix Analysis and Applications
A framework for unifying reordering transformations
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Specification and design of embedded systems
Specification and design of embedded systems
A polynomial time algorithm for counting integral points in polyhedra when the dimension is fixed
Mathematics of Operations Research
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Background memory area estimation for multidimensional signal processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Affine-by-statement scheduling of uniform and affine loop nests over parametric domains
Journal of Parallel and Distributed Computing
Parallel Computing - Special issue on applications: parallel processing and multimedia
Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Parametric Analysis of Polyhedral Iteration Spaces
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Generation of Efficient Nested Loops from Polyhedra
International Journal of Parallel Programming - Special issue on instruction-level parallelism and parallelizing compilation, part 2
Exact memory size estimation for array computations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing memory requirements of nested loops for embedded systems
Proceedings of the 38th annual Design Automation Conference
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Dependence Analysis for Supercomputing
Dependence Analysis for Supercomputing
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Storage Management Programmable Process
Storage Management Programmable Process
A Layout-Conscious Iteration Space Transformation Technique
IEEE Transactions on Computers
Array recovery and high-level transformations for DSP applications
ACM Transactions on Embedded Computing Systems (TECS)
An Exact Method for Analysis of Value-based Array Data Dependences
Proceedings of the 6th International Workshop on Languages and Compilers for Parallel Computing
Storage Size Reduction by In-place Mapping of Arrays
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Advanced copy propagation for arrays
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Data Reuse Exploration Techniques for Loop-Dominated Applications
Proceedings of the conference on Design, automation and test in Europe
Low-power design of turbo decoder with exploration of energy-throughput trade-off
Compilers and operating systems for low power
Storage requirement estimation for optimized design of data intensive applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Code Generation in the Polyhedral Model Is Easier Than You Think
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Lattice-Based Memory Allocation
IEEE Transactions on Computers
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Memory size computation for multimedia processing applications
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Global memory optimisation for embedded systems allowed by code duplication
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Formal model of data reuse analysis for hierarchical memory organizations
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast memory footprint estimation based on maximal dependency vector calculation
Proceedings of the conference on Design, automation and test in Europe
Signal-to-Memory Mapping Analysis for Multimedia Signal Processing
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Computation of storage requirements for multi-dimensional signal processing applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transformation to dynamic single assignment using a simple data flow analysis
APLAS'05 Proceedings of the Third Asian conference on Programming Languages and Systems
Experiences with enumeration of integer projections of parametric polytopes
CC'05 Proceedings of the 14th international conference on Compiler Construction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data dependency size estimation for use in memory optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On minimizing register usage of linearly scheduled algorithms with uniform dependencies
Computer Languages, Systems and Structures
Architecture exploration for efficient data transfer and storage in data-parallel applications
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
Enhancing non-linear kernels by an optimized memory hierarchy in a high level synthesis flow
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ASAM: Automatic architecture synthesis and application mapping
Microprocessors & Microsystems
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The storage requirements in data-dominated signal processing systems, whose behavior is described by array-based, loop-organized algorithmic specifications, have an important impact on the overall energy consumption, data access latency, and chip area. This paper gives a tutorial overview on the existing techniques for the evaluation of the data memory size, which is an important step during the early stage of system-level exploration. The paper focuses on the most advanced developments in the field, presenting in more detail (1) an estimation approach for non-procedural specifications, where the reordering of the loop execution within loop nests can yield significant memory savings, and (2) an exact computation approach for procedural specifications, with relevant memory management applications --- like, measuring the impact of loop transformations on the data storage, or analyzing the performance of different signal-to-memory mapping models. Moreover, the paper discusses typical memory management trade-offs --- like, for instance, between storage requirement and number of memory accesses --- taken into account during the exploration of the design space by loop transformations in the system specification.