VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low power implementation of a turbo-decoder on programmable architectures
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Memory optimization of MAP turbo decoder algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power storage cycle budget distribution tool support for hierarchical graphs
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Journal of Signal Processing Systems
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Turbo coding has become an attractive scheme for design of current communication systems, providing near optimal bit error rates for data transmission at low signal to noise ratios. However, it is as yet unsuitable for use in high data rate mobile systems owing to the high energy consumption of the decoder scheme. Due to the data dominated nature of the decoder, a memory organization providing sufficient bandwidth is the main bottleneck for energy. We have systematically optimized the memory organization's energy consumption using our Data Transfer and Storage Exploration methodology. This chapter discusses the exploration of the energy versus throughput trade-off for the turbo decoder module, which was obtained using our storage bandwidth optimization tool.