Low-power design of turbo decoder with exploration of energy-throughput trade-off
Compilers and operating systems for low power
Energy Efficient VLSI Architecture for Linear Turbo Equalizer
Journal of VLSI Signal Processing Systems
Design and implementation of low-energy turbo decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI Architectural design tradeoffs for sliding-window Log-MAP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory sub-banking scheme for high throughput MAP-based SISO decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power turbo/Viterbi decoder for 3GPP2 applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
Journal of Signal Processing Systems
Unified convolutional/turbo decoder design using tile-based timing analysis of VA/MAP kernel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Partial iterative decoding for binary turbo codes via cross-entropy based bit selection
IEEE Transactions on Communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architectures for sliding-window-based space-time turbo trellis code decoders
Journal of Electrical and Computer Engineering - Special issue on Implementations of Signal-Processing Algorithms for OFDM Systems
A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Turbo codes are the most recent breakthrough in coding theory. However, the decoder's implementation cost limits their incorporation in commercial systems. Although the decoding algorithm is highly data dominated, no true memory optimization study has been performed yet. We have extensively and systematically investigated different memory optimizations for the maximum a posteriori (MAP) class of decoding algorithms. It turns out that it is not possible to present one decoder structure as being optimal. In fact, there are several tradeoffs, which depend on the specific turbo code, the implementation target (hardware or software), and the selected cost function. We therefore end up with a parametric family of new optimized algorithms out of which the designer can choose. The impact of our optimizations is illustrated by a representative example, which shows a significant decrease in both decoding energy (factor 2.5) and delay (factor 1.7).