Memory sub-banking scheme for high throughput MAP-based SISO decoders

Authors:
Mayank Tiwari;Yuming Zhu;Chaitali Chakrabarti
Affiliations:
Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ;Department of Electrical Engineering, Arizona State University, Tempe, AZ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

The sliding window (SW) approach has been proposed as an effective means of reducing the memory requirements as well as the decoding latency of the maximum a posteriori (MAP) based soft-input soft-output (SISO) decoder in a Turbo decoder. In this paper, we present subbanked memory implementations (both single port and dual port) of the SW SISO decoder that achieves high throughput, low decoding latency, and reduced memory energy consumption. Our contributions include derivation of the optimal memory sub-banked structure for different SW configurations, study of the relationship between memory size and energy consumption for different SW configurations and study of the effect of number of sub-banks on the throughput/decoding latency for a given SW configuration.