Energy efficient data transfer and storage organization for a MAP turbo decoder module
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 50 Mbit/s iterative turbo-decoder
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design of low-power high-speed maximum a priori decoder architectures
Proceedings of the conference on Design, automation and test in Europe
Energy efficient turbo decoding for 3G mobile
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Application-Driven Architecture Synthesis
Application-Driven Architecture Synthesis
Vlsi Architectures For High-Speed Map Decoders
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Iterative decoding of binary block and convolutional codes
IEEE Transactions on Information Theory
IEEE Journal on Selected Areas in Communications
Energy Efficient VLSI Architecture for Linear Turbo Equalizer
Journal of VLSI Signal Processing Systems
VLSI Architectural design tradeoffs for sliding-window Log-MAP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory sub-banking scheme for high throughput MAP-based SISO decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unified convolutional/turbo decoder design using tile-based timing analysis of VA/MAP kernel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power memory-reduced traceback MAP decoding for double-binary convolutional turbo decoder
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Design of high-throughput fully parallel LDPC decoders based on wire partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 150Mbit/s 3GPP LTE turbo code decoder
Proceedings of the Conference on Design, Automation and Test in Europe
Area-efficient high-throughput MAP decoder architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architectures for sliding-window-based space-time turbo trellis code decoders
Journal of Electrical and Computer Engineering - Special issue on Implementations of Signal-Processing Algorithms for OFDM Systems
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Very large scale integration (VLSI) design methodology and implementation complexities of high-speed, low-power soft-input soft-output (SISO) a posteriori probability (APP) decoders are considered. These decoders are used in iterative algorithms based on turbo codes and related concatenated codes and have shown significant advantage in error correction capability compared to conventional maximum likelihood decoders. This advantage, however, comes at the expense of increased computational complexity, decoding delay, and substantial memory overhead, all of which hinge primarily on the well-known recursion bottleneck of the SISO-APP algorithm. This paper provides a rigorous analysis of the requirements for computational hardware and memory at the architectural level based on a tile-graph approach that models the resource-time scheduling of the recursions of the algorithm. The problem of constructing the decoder architecture and optimizing it for high speed and low power is formulated in terms of the individual recursion patterns which together form a tile graph according to a tiling scheme. Using the tile-graph approach, optimized architectures are derived for the various forms of the sliding-window and parallel-window algorithms known in the literature. A proposed tiling scheme of the recursion patterns, called hybrid tiling, is shown to be particularly effective in reducing memory overhead of high-speed SISO-APP architectures. Simulations demonstrate that the proposed approach achieves savings in area and power in the range of 4.2%-53.1% over state of the art.