VLSI architectures for SISO-APP decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trellis and Turbo Coding
A scalable LDPC decoder ASIC architecture with bit-serial message exchange
Integration, the VLSI Journal
Factor graphs and the sum-product algorithm
IEEE Transactions on Information Theory
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A min-sum iterative decoder based on pulsewidth message encoding
IEEE Transactions on Circuits and Systems II: Express Briefs
A fast LDPC encoder/decoder for small/medium codes
Microelectronics Journal
| Hi-index | 0.00 |
We present a method to design high-throughput fully parallel low-density parity-check (LDPC) decoders. With our method, a decoder's longest wires are divided into several short wires with pipeline registers. Log-likelihood ratio messages transmitted along with these pipelined paths are thus sent over multiple clock cycles, and the decoder's critical path delay can be reduced while maintaining comparable bit error rate performance. The number of registers inserted into paths is estimated by using wiring information extracted from initial placement and routing information with a conventional LDPC decoder, and thus only necessary registers are inserted. Also, by inserting an even number of registers into the longer wires, two different codewords can be simultaneously decoded, which improves the throughput at a small penalty in area. We present our design flow as well as post-layout simulation results for several versions of a length-1024, (3,6)-regular LDPC code. Using our technique, we achieve a maximum uncoded throughput of 13.21 Gb/s with an energy consumption of 0.098 nJ per uncoded bit at Eb/No= 5 dB. This represents a 28% increase in throughput, a 30% decrease in energy per bit, and a 1.6% increase in core area with respect to a conventional parallel LDPC decoder, using a 90-nm CMOS technology.