Good Codes Based on Very Sparse Matrices
Proceedings of the 5th IMA Conference on Cryptography and Coding
Design of high-throughput fully parallel LDPC decoders based on wire partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Efficient encoding of low-density parity-check codes
IEEE Transactions on Information Theory
IEEE Transactions on Information Theory
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Although Low-Density Parity-Check (LDPC) codes perform admirably for large block sizes - being mostly resilient to low levels of channel SNR and errors in channel equalization - real time operation and low computational effort require small and medium sized codes, which tend to be affected by these two factors. For these small to medium codes, a method for designing efficient regular codes is presented and a new technique for reducing the dependency of correct channel equalization, without much change in the inner workings or architecture of existing LDPC decoders is proposed. This goal is achieved by an improved intrinsic Log-Likelihood Ratio (LLR) estimator in the LDPC decoder - the ILE-Decoder, which only uses LDPC decoder-side information gathered during standard LDPC decoding. This information is used to improve the channel parameters estimation, thus improving the reliability of the code correction, while reducing the number of required iterations for a successful decoding. Methods for fast encoding and decoding of LDPC codes are presented, highlighting the importance of assuring low encoding/decoding latency with maintaining high throughput. The assumptions and rules that govern the estimation process via subcarrier corrected-bit accounting are presented, and the Bayesian inference estimation process is detailed. This scheme is suitable for application to multicarrier communications, such as OFDM. Simulation results in a PLC-like environment that confirm the good performance of the proposed LDPC coder/decoder are presented.