A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes

Authors:
Yeong-Luh Ueng;Chung-Jay Yang;Kuan-Chieh Wang;Chun-Jung Chen
Affiliations:
Department of Electrical Engineering and the Institute of Communications Engineering, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Macronix International Company, Ltd., Hsinchu, Taiwan and College of Electrical Engineering and Computer Science, National Tsing Hua University, Hsinchu, Taiwan;MStar Semiconductor, Inc., Hsinchu, Taiwan and College of Electrical Engineering and Computer Science, National Tsing Hua University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Year:
2010

Citing 15
Cited 1

Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels

ICCD '03 Proceedings of the 21st International Conference on Computer Design
Layered Decoding of Non-Layered LDPC Codes

DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Reconfigurable Shuffle Network Design in LDPC Decoders

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Low complexity LDPC code decoders for next generation standards

Proceedings of the conference on Design, automation and test in Europe
A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Integration, the VLSI Journal
Efficient shuffle network architecture and application for WiMAX LDPC decoders

IEEE Transactions on Circuits and Systems II: Express Briefs
Decoder design for RS-based LDPC codes

IEEE Transactions on Circuits and Systems II: Express Briefs
Design of high-throughput fully parallel LDPC decoders based on wire partitioning

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-throughput LDPC decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fully Parallel Stochastic LDPC Decoders

IEEE Transactions on Signal Processing
Good error-correcting codes based on very sparse matrices

IEEE Transactions on Information Theory
Iterative Decoding With Replicas

IEEE Transactions on Information Theory

LDPC decoder with an adaptive wordwidth datapath for energy and BER co-optimization

VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check matrix can be adopted in the design of configurable permutators. A partially parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multimode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in the efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and hence increase the maximum operating frequency. In addition, shuffled message-passing decoding is adopted, since fewer iterations can be used to achieve the desired bit-error-rate performance. In order to demonstrate the usefulness of the proposed flexible-permutator-based architecture, one single-mode rate-0.84 decoder and two multimode decoders whose code rates range between 0.79 and 0.93 have been implemented. These decoders can achieve multigigabit-per-second throughput. Using the proposed architecture to support lower rate RS-LDPC codes, e.g., rate-0.568 code, is also investigated.