Configurable LDPC Decoder Architectures for Regular and Irregular Codes
Journal of Signal Processing Systems
High-throughput layered decoder implementation for quasi-cyclic LDPC codes
IEEE Journal on Selected Areas in Communications - Special issue on capaciyy approaching codes
Design of a multimode QC-LDPC decoder based on shift-routing network
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Journal on Selected Areas in Communications - Special issue on realizing GBPS wireless personal area networks
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A generic scalable architecture for min-sum/offset-min-sum unit for irregular/regular LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes
Microprocessors & Microsystems
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
Journal of Signal Processing Systems
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
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For some time now, configurable computing has been hailed as the future for application-specific architectures. The purported advantages are well-known: the increasing NRE cost of chip fab is avoided, the same platform can be used for a variety of applications, ...