A Scalable Architecture for LDPC Decoding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
A recursive approach to low complexity codes
IEEE Transactions on Information Theory
Quasicyclic low-density parity-check codes from circulant permutation matrices
IEEE Transactions on Information Theory
LDPC block and convolutional codes based on circulant matrices
IEEE Transactions on Information Theory
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Many recent reconfigurable/multi-mode quasi-cyclic low density parity check (QC-LDPC) decoder designs have shown appealing implementation results in the literature. However, most of them are based on datapath multiplexing techniques with ad hoc matrix arrangement. There is still room for further interconnection reduction, throughput enhancement, and a more sophisticated early termination scheme. In this paper, we will focus on these issues and present a two-level design approach, which optimizes the design at (1) matrix merging level, and (2) module design level. First, direct multiplexing datapaths between multiple modes leads to great overhead on wiring complexity. In order to mitigate this problem, we merge multiple parity check matrices by proposing an efficient algorithm at matrix merging level, which helps to minimize multiplexer and wiring overhead. Second, for efficient decoding issues, we propose two design techniques at module design level. One is data wrapping scheme. It enhances the decoding throughput by using the data-wrapped memory with the proposed reconfigurable data-switching circuits (R-DSC) to conquer the data alignment problem and achieve multi-mode reconfigurability. The other is the adaptive early termination (AET) scheme. It can save the unnecessary decoding procedures under both high-SNR and low-SNR regions. Finally, to verify our design approach, we implement a triple-mode LDPC decoder chip which is compatible to IEEE 802.11n standard by using UMC 90 nm CMOS technology. This chip only occupies 3.32 mm2 and features high core utilization up to 70% with low power dissipation of 135.3 mW. The prototyping chip not only validates the proposed approach, but also outperforms the state-of-the-art QC-LDPC decoders for IEEE 802.11n systems.