Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Non-fractional parallelism in LDPC decoder implementations
Proceedings of the conference on Design, automation and test in Europe
Extended layered decoding of LDPC codes
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Decoder design for RS-based LDPC codes
IEEE Transactions on Circuits and Systems II: Express Briefs
A memory efficient FPGA implementation of quasi-cyclic LDPC decoder
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders
Journal of Signal Processing Systems
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Low Density Parity Check (LDPC) codes offer excellent error correcting performance. However, current implementations are not capable of achieving the performance required by next generation storage and telecom applications. Extrapolation of many of those designs is not possible because of routing congestions. This article proposes a new architecture, based on a redefinition of a lesser-known LDPC decoding algorithm. As random LDPC codes are the most powerful, we abstain from making simplifying assumptions about the LDPC code which could ease the routing problem. We avoid the routing congestion problem by going for multiple independent sequential decoding machines, each decoding separate received codewords. In this serial approach the required amount of memory must be multiplied by the large number of machines. Our key contribution is a check node centric reformulation of the algorithm which gives huge memory reduction and which thus makes the serial approach possible.