Multi-Gb/s LDPC code design and implementation

Authors:
Jin Sha;Zhongfeng Wang;Minglun Gao;Li Li
Affiliations:
Institute of VLSI Design, KLAPEM, Nanjing University, Nanjing, China;School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR;Institute of VLSI Design, KLAPEM, Nanjing University, Nanjing, China;Institute of VLSI Design, KLAPEM, Nanjing University, Nanjing, China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC) design (in 0.18- µm CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations.