A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Disclosing the LDPC code decoder design space
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Layered Decoding of Non-Layered LDPC Codes
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Proceedings of the 13th international symposium on Low power electronics and design
A case study in reliability-aware design: a resilient LDPC code decoder
Proceedings of the conference on Design, automation and test in Europe
Optimum LDPC decoder: a memory architecture problem
Proceedings of the 46th Annual Design Automation Conference
Fast convergence algorithm for decoding of low density parity check codes
WSEAS TRANSACTIONS on COMMUNICATIONS
A compact 1.1-Gb/s encoder and a memory-based 600-Mb/s decoder for LDPC convolutional codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
A multimode shuffled iterative decoder architecture for high-rate RS-LDPC codes
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An energy efficient layered decoding architecture for LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Gb/s LDPC code design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Flexible LDPC/Turbo Decoder Architecture
Journal of Signal Processing Systems
Serial scheduling algorithm of LDPC decoding
ICHIT'11 Proceedings of the 5th international conference on Convergence and hybrid information technology
A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes
Microprocessors & Microsystems
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
| Hi-index | 0.00 |
This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture.