Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Layered Decoding of Non-Layered LDPC Codes
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Techniques for the decoding of low density parity check codes: efficient simulation, algorithm improvement and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes
Journal of Signal Processing Systems
Hi-index | 0.00 |
Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, we present a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme. The amount of achievable memory bypassing depends on the decoding order of the layers. We formulate the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution. We also present the corresponding architecture which combines some of memory components and results in reduction of memory area. The proposed decoder was implemented in TSMC 0.18 µm CMOS process. Experimental results show that for a LDPC decoder targeting IEEE 802.11n specification, the amount of memory access values can be reduced by 12.9-19.3% compared with the state-of-the-art design. At the same time, 95.6%-100% hardware utilization rate is achieved.