A Scalable Architecture for LDPC Decoding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)
Proceedings of the 42nd annual Design Automation Conference
Low complexity LDPC code decoders for next generation standards
Proceedings of the conference on Design, automation and test in Europe
Non-fractional parallelism in LDPC decoder implementations
Proceedings of the conference on Design, automation and test in Europe
Massive parallel LDPC decoding on GPU
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Proceedings of the 13th international symposium on Low power electronics and design
Parallel LDPC Decoding on the Cell/B.E. Processor
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
How GPUs can outperform ASICs for fast LDPC decoding
Proceedings of the 23rd international conference on Supercomputing
Improved layered min-sum decoding algorithm for low density parity check codes
MUSP'09 Proceedings of the 9th WSEAS international conference on Multimedia systems & signal processing
Fast convergence algorithm for decoding of low density parity check codes
WSEAS TRANSACTIONS on COMMUNICATIONS
Conflict resolution by matrix reordering for DVB-T2 LDPC decoders
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
A novel LDPC decoder for DVB-S2 IP
Proceedings of the Conference on Design, Automation and Test in Europe
An energy efficient layered decoding architecture for LDPC decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and Finite Precision Optimization for Layered LDPC Decoders
Journal of Signal Processing Systems
Improvements on the design and implementation of DVB-S2 LDPC decoders
Computers and Electrical Engineering
A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes
Microprocessors & Microsystems
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems
ACM Transactions on Embedded Computing Systems (TECS)
Design space of flexible multigigabit LDPC decoders
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
| Hi-index | 0.01 |
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) algorithm is gaining increased attention in communication standards and literature. The new Digital Video Broadcast via Satellite standard (DVB-S2) is the first broadcast standard to include a LDPC-code, and the first implementations are available. In our investigation of generic LDPC-implementations we found that scalable sub-block parallelism enables efficient implementations for a wide range of applications. For the DVB-S2 case, using sub-block parallelism we obtain half the chip-size of known solutions. For the required performance in the normative configurations for the broadcast service (90 Mbps), the area is even 1/3 compared to the smallest published decoder.