Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Low cost LDPC decoder for DVB-S2
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Layered Decoding of Non-Layered LDPC Codes
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and Finite Precision Optimization for Layered LDPC Decoders
Journal of Signal Processing Systems
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Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the existence of multiple diagonal matrices in the DVB-T2 parity check matrix structure. We illustrate how the reordering of the matrix reduces the number of conflicts, at the cost of limiting the level of parallelism. We then propose a parity extending process to solve the remaining conflicts. Fixed point simulation results show coherent performance without modifying the layered architecture.